Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation Experimental results show that the proposed four methods save up to 20% of clock tree capacitance loading Beyond controlling slew to suppress supply-voltage-variation-induced skew, we also discuss the strategies of clock tree synthesis under variant variation scenarios and the limitations of the ISPD 2010 benchmark
Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation Fig 5 Length-based buffer insertion (a) Flow of length-based buffer insertion; (b) a symmetric topology is adopted; (c) inserting buffers on all branches; (d) inserting buffers by a distance d; (e) enlarging the buffer size - "Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation"
3Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation We observe that slow slew amplifies supply voltage variation, which induces larger path delay variation and skew uncertainty To obtain the optimality, we formulate a symmetric clock tree synthesis as a mathematical programming problem in which the slew effect is considered by an NLDM-like cell delay variation model
Clock tree synthesis considering slew effect on supply voltage variation We observe that slow slew amplifies supply voltage variation, which induces larger path delay variation and skew uncertainty To obtain the optimality, we formulate a symmetric clock tree synthesis as a mathematical programming problem in which the slew effect is considered by an NLDM-like cell delay variation model
Clock tree synthesis considering slew effect on supply voltage variation Experimental results show that the proposed four methods save up to 20% of clock tree capacitance loading Beyond controlling slew to suppress supply-voltage-variation-induced skew, we also discuss the strategies of clock tree synthesis under variant variation scenarios and the limitations of the ISPD 2010 benchmark
Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation The refinement shifts stages of small input slew toward the root It reduces capacitance loading near leaf level (a) An asymmetric tree without solution refinement; (b) an asymmetric tree with solution refinement - "Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation"